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This work presents a first common gate continuous time linear equalizer (CG-CTLE) with charge mode adaptation in 1.1 V, 65 nm CMOS technology. The proposed equalizer is realized with a common gate topology and offers an input impedance of 50 Ω. It also acts as a first stage of current modereceiver and is made adaptive to varying channel loss. Therefore, the need for an external...
In this paper, we analyze the impact of voltage, temperature and body-biasing on the detection of resistive short defects for low-VT (LVT) and regular-VT (RVT) configurations of a 28nm UTBB FDSOI (Ultra Thin Body & BOX Fully Depleted Silicon-On-Insulator) technology. We implemented a similar design in each configuration and compared their electrical behaviors with the same resistive short...
In the present paper, an operational amplifier (Op-Amp) topology that achieves high-gain and low-power dissipation is designed and analyzed. The design uses a current mirror with a class-A output stage having capacitive Miller compensation. The low power operational amplifier is the main active power consuming block. The proposed Op-Amp operates at ±0.75V supply voltage and consumes a total...
Approximate computing techniques have paved new paths to get substantial improvement in speed and power efficiency by making a trade-off with the accuracy of computations in inherently error tolerant applications, like from image and video processing domains. The accuracy requirements of various applications can differ from each other. Even within a same application different computationscan have...
Nowadays, typical (memory) designers add design margins to compensate for uncertainties, however, this may be overestimated leading to yield loss, or underestimated leadingto reduced reliability designs. Accurate quantification of alluncertainties is therefore critical to provide high quality andoptimal designs. These uncertainties are caused by zero-timevariability (due to process variability), and...
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